Erasable programmable read-only memory (EPROM), electrically erasable read-only memory (EEPROM), and flash memory devices consist of a plurality of gate structures. These gate structures generally comprise a control gate and a floating gate that is positioned between the control gate and a substrate. The floating gate is a conductive layer normally fabricated of a polysilicon material. The floating gate is not attached to any electrodes or power sources and is itself generally surrounded by an insulation material.
The operation of EEPROM non-volatile memory devices, such as a floating gate tunnel oxide (FLOTOX) EEPROM, is dependent upon the charge stored in the floating gate at the threshold voltage needed to represent information stored in these devices.
The performance of EEPROM devices typically includes a performance specification or rating of the programming speed that influences the speed of erase and write operations. The speed is typically limited by the rate at which electrons can be pumped into (writing) and out of (erasing) the device without causing damage to the device. Typically, erasing and writing operations must be capable of operating within 1 msec at a specified applied voltage.
As the dimensions of memory devices continue to be reduced, the thickness of each of the layers must also be reduced. While, for example, a thinner tunneling oxide layer may increase data writing and erasing efficiency as well as speed, smaller tunneling oxide layers may be more susceptible to damage upon exposure to recording or erasing energies. There remains a need in the art for improved processing strategies for responding to the demands created by the drive to achieve even smaller memory devices.
Additionally, smaller dimensions may require greater uniformity in memory device layers to ensure the device works for its intended purpose. There remains a need in the art for memory devices and processing techniques to improve the product and operational performance of such devices.